PI6ULS5V9617AUE

The PI6ULS5V9617A device enables the system designer to isolate two halves of a bus for both voltage and capacitance by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines. This allows for accommodating more I2C devices or longer trace length . Furthermore, the PI6ULS5V9617A has port A drivers with adjustable voltage, eliminating static offset voltage and accommodating smaller voltage swings of lower voltage logic. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A, allowing for isolation of the two halves of the bus for voltage differences . In summary, the PI6ULS5V9617A device offers bidirectional buffering for data and clock lines, adjustable voltage drivers, and control over driver activation, enabling the system designer to isolate two halves of a bus for both voltage and capacitance requirements

The PI6ULS5V9617A device supports a maximum clock frequency for Fast-mode Plus (Fm+) I2C-bus or SMBus applications.

The PI6ULS5V9617A device enables voltage level translation down to as low as 0.6V without degradation of system performance. It supports up-translation/down-translation between the low voltage (0.6V) and a 2.5V, 3.3V, or 5V I2C-bus or SMBus. Additionally, all inputs and I/Os are overvoltage tolerant up to 5.5V even when the device is unpowered. The B-side drivers operate from 2.2V to 5.5V, with the output low level of the internal buffer being approximately 0.55V. The input voltage must be 90mV lower (0.45V) or even more lower than the output low level voltage. .