DS2431P+

The DS2431 has four memory pages.

The DS2431 EEPROM chip has a capacity of 1024 bits, organized as four memory pages of 256 bits each. Each page can be individually set to open (unprotected), write protected, or EPROM mode. The EEPROM array consists of 18 rows of 8 bytes each, with the first 16 rows divided equally into four memory pages of 32 bytes each. The last two rows contain protection registers and reserved bytes. The chip also has a unique 64-bit ROM registration number factory lasered into it for addressing in a multidrop, 1-Wire net environment.

The DS2431 uses a communication protocol that consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. The bus master initiates all falling edges except for the presence pulse. The DS2431 can communicate at two different speeds: standard speed and overdrive speed. If not explicitly set into overdrive mode, the DS2431 communicates at standard speed. While in overdrive mode, the fast timing applies to all waveforms. The protocol requires strict protocols to ensure data integrity.